Transcend TS128MLD64V4J Arkusz Danych Pobierz pdf (Strona 8)

184PIN DDR400 Unbuffered DIMM

1024MB With 64Mx8 CL3

Transcend Information Inc.

Parameter Symbol Min Max Unit Note

Row cycle time tRC

55 ns

Refresh row cycle time tRFC

70 ns

Row active time tRAS

40 70K ns

/RAS to /CAS delay tRCD

15 ns

Row active to Row active delay tRP

15 ns

Row active to Row active delay tRRD

10 ns

Write recovery time tWR

15 ns

Last data in to Read command tWTR

2 tCK

Clock cycle time tCK

5 10 ns 16

Clock high level width tCH

0.45 0.55 tCK

Clock low level width tCL

0.45 0.55 tCK

DQS-out access time from CK /CK tDQSCK

-0.55 0.55 ns

Output data access time from CK /CK tAC

-0.65 0.65 ns

Data strobe edge to output data edge tDQSQ

0.4 ns 13

Read Preamble tRPRE

0.9 1.1 tCK

Read Postamble tRPST

0.4 0.6 tCK

CK to valid DQS-in tDQSS

0.72 1.28 tCK

Write preamble setup time tWPRES

0 ps 5

Write preamble tWPRE

0.25 tCK

Write postamble tWPST

0.4 0.6 tCK 4

DQS falling edge to CK rising-setup time tDSS

0.2 tCK

DQS falling edge from CK rising-hold time tDSH

0.2 tCK

DQS-in high level width tDQSH

0.35 tCK

DQS-in low level width tDQSL

0.35 tCK

Address and Control input setup time tIS

0.6 ns 7~10

Address and Control input hold time tIH 0.6

ns 7~10

Data-out high-impedance time from CK, /CK tHZ - tAC max

ns 3

Data-out low-impedance time from CK, /CK tLZ tAC min

tAC max ns 3

Mode register set cycle time tMRD 2

DQ & DM setup time to DQS tDS 0.4

DQ & DM hold time to DQS tDH 0.4

DQ & DM input pulse width tDIPW 1.75

ns 9

Control &Address input pulse width for each input tIPW 2.2 ns 9

Refresh interval time tREF 7.8

us 6

1 2 3 4 5 6 7 8 9 10 11 12

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