Transcend TS128MLD64V4J Arkusz Danych Pobierz pdf (Strona 7)

184PIN DDR400 Unbuffered DIMM

1024MB With 64Mx8 CL3

Transcend Information Inc.

Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V

Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) VREF - 0.31 V

Input Differential Voltage, CK and /CK inputs VID(AC) 0.7 VDDQ + 0.6 ns

Input Crossing Point Voltage, CK and /CK inputs VIX(AC) 0.5*VDDQ - 0.2 0.5*VDDQ + 0.2

Note: 1. VIH(max)=4.2V. The overshoot voltage duration is <=3ns at VDD.

2. VIL(min)=-1.5V. The undershoot voltage duration is <=3ns at VSS

3. VID is the magnitude of the difference between the input level on CK and the input on /CK

4. The Value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC

level of the same.

AC OPERATING TEST CONDITIONS (VDD=2.6, VDDQ=2.6, TA=0 to 70°C)

Parameter Value Unit Note

Input reference voltage for Clock 0.5*VDDQ V

Input signal maximum peak swing 1.5 V

Input Levels (VIH/VIL) VREF+0.31/VREF-0.31 V

Input timing measurement reference level VREF V

Output timing measurement reference level Vtt V

Output load condition See Load Circuit

ZO=50ohm

VTT=0.5*VDDQ

RT=50ohm

LOAD

=30pF

Output

Output Load circuit

VREF

=0.5*VDDQ

Input/Output CAPACITANCE

(VDD = 2.6V, VDDQ = 2.6V,TA = 25°C, f = 1MHz)

Parameter Symbol Min Max Unit

Input capacitance (A0~A12, BA0~BA1, /RAS, /CAS, /WE)

Input capacitance (CKE0, CKE1)

Input capacitance (/CS0, /CS1)

Input capacitance (CLK0, CLK1, CLK2)

Data and DQS input/output capacitance (DQ0~DQ63)

Input capacitance (DM0~DM7)

CIN1

CIN2

IN3

IN4

OUT

CIN5

AC Timming Parameters & Specifications

(These AC characteristics were tested on the Component)

1 2 3 4 5 6 7 8 9 10 11 12

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Transcend TS128MLD64V4J Arkusz Danych Strona 7

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