T
T
T
S
S
S
1
1
1
2
2
2
8
8
8
M
M
M
L
L
L
D
D
D
6
6
6
4
4
4
V
V
V
4
4
4
J
J
J
184PIN DDR400 Unbuffered DIMM
1024MB With 64Mx8 CL3
Transcend Information Inc.
11
Serial Presence Detect Specification
Serial Presence Detect
Byte No. Function Described
Standard
Specification
Vendor Part
0 # of Bytes Written into Serial Memory 128bytes 80
1 Total # of Bytes of S.P.D Memory 256bytes 08
2 Fundamental Memory Type DDR SDRAM 07
3 # of Row Addresses on this Assembly 13 0D
4 # of Column Addresses on this Assembly 11 0B
5 # of Module Rows on this Assembly 2 bank 02
6 Data Width of this Assembly 64bits 40
7 Data Width of this Assembly 0 00
8 VDDQ and Interface Standard of this Assembly SSTL-2 04
9 DDR SDRAM Cycle Time at CAS Latency=3 5ns 50
10 DDR SDRAM Access Time from Clock at CL=3
±0.65ns
65
11 DIMM configuration type (non-parity, Parity, ECC) Non ECC 00
12 Refresh Rate Type 7.8us/Self Refresh 82
13 Primary DDR SDRAM Width X8 08
14 Error Checking DDR SDRAM Width X0 00
15
Min Clock Delay for Back to
Back Random Column Address
tCCD=1CLK 01
16 Burst Lengths Supported 2,4,8 0E
17 # of banks on each DDR SDRAM device 4 bank 04
18 CAS Latency supported 2.5,3 18
19 CS Latency 0 CLK 01
20 WE Latency 1 CLK 02
21 DDR SDRAM Module Attributes
Differential
Clock Input
20
22 DDR SDRAM Device Attributes: General Fast/concurrent AP C0
23 DDR SDRAM Cycle Time CL=2.5 6ns 60
24 DDR SDRAM Access from Clock CL=2.5
±0.7ns
70
25 DDR SDRAM Cycle Time CL=2.0 0 0
26 DDR SDRAM Access from Clock CL=2.0 0 0
27 Minimum Row Precharge Time (tRP) 15ns 3C
28 Minimum Row Active to Row Activate delay (tRRD) 10ns 28
29 Minimum RAS to CAS Delay (tRCD) 15ns 3C
30 Minimum active to Precharge time (tRAS) 40ns 28
31 Module ROW density 512MB 80
32 Command/Address Input Setup Time 0.6ns 60
33 Command/Address Input Hold Time 0.6ns 60
34 Data Signal Input Setup Time 0.4ns 40
35 Data Signal Input Hold Time 0.4ns 40
36-40 Superset Information - 00
41
DDR SDRAM Minimum Active to Active/Auto Refresh
Time(tRC)
55ns 37
42
DDR SDRAM Minimum Auto-Refresh to
70ns 46
(11 strony)
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