Transcend TS32MDR72V3F Arkusz Danych Pobierz pdf (Strona 6)

184PIN DDR333 Registered DIMM

256MB With 32Mx8 CL2.5

Transcend Information Inc.

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, VDD=2.7V TA = 10°C)

Parameter Symbol Max. Unit Note

Operating current - One bank Active-Precharge;

tRC=tRCmin; tCK= tCK min

DQ, DM and DQS inputs changing twice per clock cycle;

Address and control inputs changing once per clock cycle

IDD0

1560 mA

Operating current - One bank Active-Read-Precharge; Burst=2;

tRC=tRC min; CL=2.5; tCK=tCK min; VIN=VREF fro DQ,DQS and DM

IDD1 1790 mA

Percharge power-down standby current; All banks idle;

power –down mode; CKE = <VIL(max); tCK= tCK min

VIN = VREF

for DQ,DQS and DM

IDD2P 410

Precharge Floating standby current; CS# > =VIH(min);All banks idle;

CKE > = VIH(min); tCK=133Mhz for DDR266

Address and other control inputs changing once per clock cycle;

VIN = VREF for DQ,DQS and DM

IDD2F 980 mA

Active power - down standby current; one bank active; power-down mode; CKE<=

VIL (max); tCK = tCK min;

VIN = VREF for DQ,DQS and DM

IDD3P 700 mA

Active standby current; CS# >= VIH(min); CKE>=VIH(min);

one bank active; active - precharge; tRC=tRASmax; tCK = tCK min;

DQ, DQS and DM inputs changing twice per clock cycle; address and other control

inputs changing once per clock cycle

IDD3N 1250

Operating current - burst read; Burst length = 2; reads; continuous burst; One

bank active; address and control inputs changing once per clock cycle; CL=2.5 at

tCK = tCK min; 50% of data changing at every burst; lout = 0 mA

IDD4R 2190

Operating current - burst write; Burst length = 2; writes; continuous burst; One

bank active address and control inputs changing once per clock cycle; CL=2.5 at

tCK = tCK min ; DQ, DM and DQS inputs changing twice per clock cycle, 50% of

input data changing at every burst

IDD4W 2190 mA

Auto refresh current; tRC = tRFC(min)

IDD5 2280 mA

Self refresh current; CKE <= 0.2V;

IDD6

410 mA

Operating current - Four bank operation;

Four bank interleaving with BL=4

-Refer to the following page for detailed test condition

IDD7 3270 mA

Note:

1. Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ

loading capacitor.

1 2 3 4 5 6 7 8 9 10 11

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